计算机科学论文代写 User Interfaces Ic Compiler

计算机科学论文代写 User Interfaces Ic Compiler

5.1 Introduction

Design planning in IC Compiler provides basic floorplanning and prototyping capabilities such as dirty-netlist handling, automatic die size exploration, performing various operations with black box modules and cells, fast placement of macros and standard cells, packing macros into arrays, creating and shaping plan groups, in-place optimization, prototype global routing analysis, hierarchical clock planning, performing pin assignment on soft macros and plan groups, performing timing budgeting, converting the hierarchy, and refining the pin assignment.

Power network synthesis and power network analysis functions, applied during the feasibility phase of design planning, provide automatic synthesis of local power structures within voltage areas. Power network analysis validates the power synthesis results by performing voltage-drop and electromigration analysis. [16]

Figure 5.1 – IC Compiler Design Planning [21]

5.2 Tasks to be performed during Design Planning

• Initializing the Floorplan

• Automating Die Size Exploration

• Handling Black Boxes

• Performing an Initial Virtual Flat Placement

• Creating and Shaping Plan Groups

• Performing Power Planning

• Performing Prototype Global Routing

• Performing Hierarchical Clock Planning

• Performing In-Place Optimization

• Performing Routing-Based Pin Assignment

• Performing RC Extraction

• Performing Timing Analysis

• Performing Timing Budgeting

• Committing the Physical Hierarchy

• Refining the Pin Assignment

5.3 Initializing the Floorplan

The steps in initializing the floorplan are described below.

• Reading the I/O Constraints:

To load the top-level I/O pad and pin constraints, use the read_io_constraints command.

• Defining the Core and Placing the I/O Pads:

To define the core and place the I/O pads and pins, use the initialize_floorplan command.

• Creating Rectilinear-Shaped Blocks:

Use the initialize_rectilinear_block command to create a floorplan for rectilinear blocks from a fixed set of L, T, U, or cross-shaped templates. These templates are used to determine the cell boundary and shape of the core. To do this, use initialize_rectilinear_block -shape L|T|U|X.

• Writing I/O Constraint Information:

To write top-level I/O pad or pin constraints, use the write_io_constraints command.

Read the Synopsys Design Constraints (SDC) file (read_sdc command) to ensure that all signal paths are constrained for timing.

• Adding Cell Rows:

To add cell rows, use the add_row command.

• Removing Cell Rows:

To remove cell rows, use the cut_row command.

• Saving the Floorplan Information:

To save the floorplan information, use the write_floorplan command.

•Writing Floorplan Physical Constraints for Design Compiler Topographical Technology:

IC Compiler can now write out the floorplan physical constraints for Design Compiler

Topographical Technology (DC-T) in Tcl format. The reason for using floorplan physical constraints in the Design Compiler topographical technology mode is to accurately represent the placement area and to improve timing correlation with the post-place-and-route design. The command syntax is:

write_physical_constraints -output output_file_name -port_side [16]

Figure 5.2 – Floor Plan After Initialization [21]

5.4 Automating Die Size Exploration

This section describes how to use MinChip technology in IC Compiler to automate the processes exploring and identifying the valid die areas to determine smallest routable, die

size for your design while maintaining the relative placement of hard macros, I/O cells, and a power structure that meets voltage drop requirements. The technology is integrated into the Design Planning tool through the estimate_fp_area command. The input is a physically flat Milkyway CEL view.

5.5 Handling Black Boxes

Black boxes can be represented in the physical design as either soft or hard macros. A black box macro has a fixed height and width. A black box soft macro sized by area and utilization can be shaped to best fit the floorplan.

To handle the black boxes run the following set of commands.

set_fp_base_gate

estimate_fp_black_boxes

flatten_fp_black_boxes

create_fp_placement

place_fp_pins

create_qtm_model qtm_bb

set_qtm_technology -lib library_name

create_qtm_port -type clock $port

report_qtm_model

write_qtm_model -format qtm_bb

report_timing qtm_bb

5.6 Performing an Initial Virtual Flat Placement

The initial virtual flat placement is very fast and is optimized for wire length, congestion, and timing.

The way to perform an initial virtual flat placement is described below.

• Evaluating Initial Hard Macro Placement:

No straightforward criteria exist for evaluating the initial hard macro placement. Measuring the quality of results (QoR) of the hard macro placement can be very subjective and often depends on practical design experience.

• Specifying Hard Macro Placement Constraints:

Different methods can be use to control the preplacement of hard macros and improve the QoR of the hard macro placement.

Creating a User-Defined Array of Hard Macros

Setting Floorplan Placement Constraints On Macro Cells

Placing a Macro Cell Relative to an Anchor Object

Using a Virtual Flat Placement Strategy

Enhancing the Behavior of Virtual Flat Placement With the macros_on_edge Switch

Creating Macro Blockages for Hard Macros

Padding the Hard Macros

• Padding the Hard Macros:

To avoid placing standard cells too close to macros, which can cause congestion or DRC violations, one can set a user-defined padding distance or keepout margin around the macros. One can set this padding distance on a selected macro’s cell instance master.During virtual flat placement no other cells will be placed within the specified distance from the macro’s edges. [16]

To set a padding distance (keepout margin) on a selected macro’s cell instance master, use the set_keepout_margin command.

• Placing Hard Macros and Standard Cells:

To place the hard macros and standard cells simultaneously, use the create_fp_placement command.

• Performing Floorplan Editing:

IC Compiler performs the following floorplan editing operations.

Creating objects

Deleting objects

Undoing and redoing edit changes

Moving objects

Changing the way objects snap to a grid

Aligning movable objects

5.7 Creating and Shaping Plan Groups

This section describes how to create plan groups for logic modules that need to be physically implemented. Plan groups restrict the placement of cells to a specific region of the core area. This section also describes how to automatically place and shape objects in a design core, add padding around plan group boundaries, and prevent signal leakage and maintain signal integrity by adding modular block shielding to plan groups and soft macros.

The following steps are covered for Creating and Shaping Plan Groups.

• Creating Plan Groups:

To create a plan group, create_plan_groups command.

To remove (delete) plan groups from the current design, use the remove_plan_groups command.

• Automatically Placing and Shaping Objects In a Design Core:

Plan groups are automatically shaped, sized, and placed inside the core area based on the distribution of cells resulting from the initial virtual flat placement. Blocks (plan groups, voltage areas, and soft macros) marked fix remain fixed; the other blocks, whether or not they are inside the core, are subject to being moved or reshaped.

To automatically place and shape objects in the design core, shape_fp_blocks command.

• Adding Padding to Plan Groups:

To prevent congestion or DRC violations, one can add padding around plan group

boundaries. Plan group padding sets placement blockages on the internal and external

edges of the plan group boundary. Internal padding is equivalent to boundary spacing in the core area. External padding is equivalent to macro padding.

To add padding to plan groups, create_fp_plan_group_padding command.

To remove both external and internal padding for the plan groups, use the remove_fp_plan_group_padding command.

• Adding Block Shielding to Plan Groups or Soft Macros:

When two signals are routed parallel to each other, signal leakage can occur between the signals, leading to an unreliable design. One can protect signal integrity by adding modular block shielding to plan groups and soft macros. The shielding consists of metal rectangles that are created around the outside of the soft macro boundary in the top level of the design, and around the inside boundary of the soft macro.

To add block shielding for plan groups or soft macros, use the create_fp_block_shielding command.

To remove the signal shielding created by modular block shielding, use the remove_fp_block_shielding command. [16]