计算机科学论文代写 User Interfaces Ic Compiler
计算机科学论文代写 User Interfaces Ic Compiler
Figure 4.1 – IC Compiler Design Flow [21]
For most designs, if the place_opt, clock_opt, and route_opt steps are followed, IC Compiler will provide optimal results. You can use IC Compiler to efficiently perform chip-level design planning, placement, clock tree synthesis and routing on designs with moderate timing and congestion challenges.
To further improve the quality of results for your design you can use additional commands and switches for placement, clock tree synthesis, and routing steps that IC Compiler provides.
IC Compiler design flow involves execution of following steps:
1. Set up and prepare the libraries and the design data.
2. Perform design planning and power planning.
-Design planning is to perform necessary steps to create a floorplan, determine the size of the design, create the boundary and core area, create site rows for the placement of standard cells, set up the I/O pads.
-Power planning, is to perform necessary steps to create a power plan to meet the power budget and the target leakage current.
3. Perform placement and optimization.
IC Compiler placement and optimization uses enhanced placement and synthesis technologies to generate a legalized placement for leaf cells and an optimized design, which addresses and resolves timing closure issues for the provided design. You can supplement this functionality by optimizing for power, recovering area for placement, minimizing congestion, and minimizing timing and design rule violations.
To perform placement and optimization, use the place_opt core command (or from GUI choose “Placement” menu and then “Core Placement and Optimization” sub-menu).
4. Perform clock tree synthesis and optimization.
To perform the clock tree synthesis and optimization phase, use the command clock_opt (or
choose Clock > Core Clock Tree Synthesis and Optimization in the GUI).
IC Compiler clock tree synthesis and embedded optimization solve complicated clock tree synthesis problems, such as blockage avoidance and the correlation between preroute and postroute data. Clock tree optimization improves both clock skew and clock insertion delay by performing buffer sizing, buffer relocation, gate sizing, gate relocation, level adjustment, reconfiguration, delay insertion, dummy load insertion, and balancing of interclock delays.
5. Perform routing and postroute optimization.
To perform routing and postroute optimization, use the route_opt core command (or choose Route > Core Routing and Optimization in the GUI).
As part of routing and postroute optimization, IC Compiler performs global routing, detail routing, track assignment, topological optimization, and engineering change order (ECO) routing. For most designs, the default routing and postroute optimization setup produces optimal results. If necessary, you can supplement this functionality by optimizing routing patterns and reducing crosstalk or by customizing the
routing and postroute optimization functions for special needs.
6. Perform chip finishing and design for manufacturing tasks.
IC Compiler provides chip finishing and design for manufacturing and yield capabilities that you can apply throughout the various stages of the design flow to address process design issues encountered during chip manufacturing.
7. Save the design.
Save your design in the Milkyway format. This format is the internal database format used by IC Compiler to store all the logical and physical information about a design. [16]
4.3 How to Invoke the IC Compiler
1. Log in to the UNIX environment with the user id and password .
2. Start IC Compiler from the UNIX promt:
UNIX$ icc_shell
The xterm unix prompt turns into the IC Compiler shell command prompt.
3. Start the GUI.
icc_shell> start_gui
This window can display schematics and logical browsers, among other things, once a design is loaded.
4.4 Preparing the Design
IC Compiler uses a Milkyway design library to store design and its associated library information. This section describes how to set up the libraries, create a Milkyway design library, read your design, and save the design in Milkyway format.
These steps are explained in the following sections:
• Setting Up the Libraries
• Setting Up the Power and Ground Nets
• Reading the Design
• Annotating the Physical Data
• Preparing for Timing Analysis and RC Calculation
• Saving the Design